1. Field of the Invention
The present invention relates to methods and equipment for forming dielectric stacks in integrated circuits, and particularly to forming a thin oxide interfacial layer under a high-k material.
2. Description of the Related Art
Thin dielectric layers are often desired over semiconductor surfaces in fabricating integrated circuits. Conventional gate dielectrics are formed of high quality silicon dioxide and are typically referred to as xe2x80x9cgate oxidexe2x80x9d layers. Such layers are typically grown from a single crystal silicon wafer or epitaxial silicon layer. The gate oxide capacitively couples the gate electrode to the channel region between the source and the drain regions in a typical transistor.
As integrated circuits have become smaller, it has become desirable to reduce the thickness of the gate oxide layer. However, ultra thin gate oxides (e.g., less than 5 nm) have been found to exhibit high defect densities, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects. Such high defect densities lead to leakage currents through the gate dielectric and rapid device breakdown that is unacceptable for circuit designs with less than 0.25 xcexcm gate spacing, i.e., sub-quarter-micron technology.
While care under laboratory conditions can be used to control defect densities, such control has been difficult to achieve under commercial volume fabrication conditions. Moreover, even if the integrity of the oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of gate oxide. At high fields, direct tunneling dominates over Fowler-Nordheim tunneling, and largely determines oxide scaling limits. These scaling limits have been estimated at about 2 nm for logic circuits, and about 3 nm for more leakage-sensitive memory arrays in dynamic random access memory (DRAM) circuits. See, e.g., Hu et al., xe2x80x9cThin Gate Oxides Promise High Reliability,xe2x80x9d SEMICONDUCTOR INTERNATIONAL (July 1998), pp. 215-222.
Theoretically, incorporating materials with a higher permittivity than SiO2 into the gate dielectric opens the door to further device scaling. Due to their higher dielectric constant, such materials can exhibit the same capacitance as a thinner silicon dioxide layer, such that a lower equivalent oxide thickness can be achieved without tunnel-limited behavior. Another advantage of some high dielectric materials is their diffusion barrier properties, such as resistance to boron penetration, and their high thermal conductivity.
The use of high permittivity oxides, such as Al2O3 and ZrO2 as gate dielectrics has been the focus of a great deal of recent work. The deposition of thin films from high-k materials has been accomplished by numerous techniques, including chemical vapor deposition (CVD), reactive sputtering, molecular beam epitaxy (MBE) and atomic layer deposition (ALD). ALD is a very promising method because it provides control of film thickness and composition at an atomic level leading to uniform, highly conformal deposition.
ALD is a self-limiting process, whereby alternated pulses of reaction precursors saturate a substrate surface and leave no more than one monolayer of material per pulse. The deposition conditions and precursors are selected to ensure self-saturating reactions, such that an adsorbed layer in one pulse leaves a surface termination that is non-reactive with the gas phase reactants of the same pulse. A subsequent pulse of different reactants reacts with the previous termination to enable continued deposition. Thus, each cycle of alternated pulses leaves no more than about one molecular layer of the desired material. The principles of ALD type processes have been presented by T. Suntola, e.g. in the Handbook of Crystal Growth 3, Thin Films and Epitaxy, Part B: Growth Mechanisms and Dynamics, Chapter 14, Atomic Layer Epitaxy, pp. 601-663, Elsevier Science B.V. 1994, the disclosure of which is incorporated herein by reference.
In a typical ALD process for depositing metal oxides, one deposition cycle comprises exposing the substrate to a metal precursor, removing unreacted first reactant and reaction byproducts from the reaction chamber, exposing the substrate to an oxygen precursor followed by a second removal step. It has been suggested that a major problem in the ALD of high-k metal oxides on silicon is that at the beginning of the process the silicon surface is covered with only a monolayer of metal when it is exposed to the oxygen source. Thus, under typical growth conditions a layer of SiO2 is formed. With each subsequent cycle this layer tends to grow and limits the achievable capacitance. A number of solutions to this potential problem have been proposed. For example, it has been found to be possible to deposit aluminum oxide on silicon substrates without creating an interfacial silicon oxide layer by using metal alkoxides, which serve as both a metal and oxygen source in reacting with another metal compound (Ritala et al. Science 288:319-321 (2000)).
However, it has also been suggested that a very thin silicon oxide interface layer is desirable, even for alternative gate dielectric materials, as it provides superior silicon/oxide interface characteristics. For example, Yang et al. (Humantech Thesis Prize, Samsung Electronics (1999)) showed that the presence of a thin silicon oxide layer between aluminum oxide and the silicon substrate produced a superior gate dielectric compared to aluminum oxide alone. Similarly, forming silicon nitride over thin oxide layers has been found to reduce defect densities while considerably lowering overall gate dielectric equivalent oxide thickness. See, e.g., Kim et al., xe2x80x9cUltra Thin ( less than 3 nm) High Quality Nitride/Oxide Stack Gate Dielectrics Fabricated by In-Situ Rapid Thermal Processing,xe2x80x9d IEDM 97 (1997), pp. 463-466. Methods of depositing a thin interfacial oxide layer between the substrate and a high-k material have been described, for example in U.S. Pat. No. 6,144,060 and in U.S. patent application Ser. No. 09/471,761 filed Dec. 23, 1999.
Prior to thermally growing silicon oxide, the silicon surface is desirably cleaned to avoid contamination and produce superior electrical properties. Among other things, the surface is generally cleaned of a naturally forming oxide known as xe2x80x9cnative oxide.xe2x80x9d As is well known in the art, native oxide forms naturally over bare silicon surfaces even upon exposure to clean room environments at room temperature. Typically, native oxide comprises a few angstroms of silicon oxide and therefore makes up a substantial portion of the dielectric film to be formed. While a thermal oxide can be grown through the native oxide to complete the desired dielectric layer, the quality and thickness of the native oxide are inconsistent across the silicon surface. Moreover, the native oxide that results from long transportation and/or storage is typically contaminated with impurities.
Accordingly, native oxide is often removed from the surface with dilute hydrofluoric acid (HF) baths or HF vapor etching. Dipping the wafers in a dilute HF bath cleans the silicon surface of native oxide and leaves the surface hydrogen terminated. HF vapor etching similarly cleans the silicon surface and terminates dangling silicon bonds, but the surface termination includes a substantial fluorine content.
Hydrogen termination is not very stable, particularly at elevated temperatures. The hydrogen atoms readily desorb to leave the dangling silicon bonds that tend to attract atmospheric contaminants. Even with hydrogen and fluorine termination in place, atmospheric oxidants can still diffuse through the termination layer between the HF treatment and subsequent processing. Thus, HF treatment cleans the wafer surface but leaves the surface inadequately protected for the period between cleaning and further processing.
One manner in which a clean silicon surface can be maintained for longer periods of time is to quickly grow a thin silicon oxide layer after cleaning the silicon surface. As mentioned above, an ultra thin SiO2 layer can provide improved interface characteristics between a silicon structure and high dielectric permittivity (high-k dielectric) materials. Spontaneous oxide regrowth, such as by room temperature exposure to typical oxidants like air or water, results in a very slow reaction, which is unacceptable for commercial fabrication.
As is well known, heating the wafer during oxidation can increase the oxidation rate. Unfortunately, thermal oxidation at temperatures greater than 500xc2x0 C. causes the hydrogen termination left by HF treatment to desorb well before temperatures reach the level at which significant oxidation takes place. In the interim, the silicon surface is left unprotected. Moreover, thermal oxidation of the initially bare silicon substrate proceeds rapidly and by mechanisms that are not well understood, as compared to latter stages during which oxidants diffuse through an already-grown portion of the silicon oxide. Accordingly, when attempting to provide oxide thicknesses appropriate for interface improvement beneath high-k materials, the oxidation is not easily controlled and can easily exceed the desired thickness. Additionally, even if an ultra thin oxide layer is effectively formed as an interfacial layer, under typical growth conditions when the subsequent high-k material is deposited the oxide layer grows further. A silicon oxide interface that is too thick results in a lower overall dielectric constant.
While it is beneficial to have an ultra thin SiO2 interfacial layer between the substrate and the high-k material, the thickness of the SiO2 interface determines the minimum thickness for the gate oxide layer. A need exists, therefore, for forming and maintaining an ultra thin SiO2 interface. Desirably, such methods should be compatible with single-wafer processing systems and sub-quarter-micron technology, yet exhibit higher yield and throughput compared to conventional techniques.
In one aspect the present invention relates to a process for forming a gate dielectric on a semiconductor substrate by forming an interfacial dielectric oxide layer on the substrate and depositing a high-k layer over the interfacial dielectric. The high-k layer is preferably deposited under conditions such that the thickness of the interfacial dielectric layer does not substantially increase.
In another aspect, the present invention relates to a method of forming a dielectric layer on a silicon substrate. The method preferably comprises growing a silicon oxide interface layer less than about 15 xc3x85 thick on the substrate and depositing a high-k material on top of the interface layer. Preferably, depositing comprises maintaining the substrate at a temperature less than about 300xc2x0 C. and supplying water vapor as an oxidizing agent. Depositing the high-k material preferably grows the interface layer by less than about 15 xc3x85, more preferably by less than about 10 xc3x85 and even more preferably by less than about 5 xc3x85.
In one embodiment depositing comprises an ALD process. The ALD process may in turn comprise a plurality of cycles, with each cycle preferably comprising: contacting the substrate with a first reactant; removing the unreacted first reactant and possible reaction byproducts from the reaction chamber; contacting the substrate with water vapor; and removing the unreacted water vapor and possible reaction byproducts from the reaction chamber.